The fabrication of integrated circuits (ICs) involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors, and the interconnection of such components. To form the features, layers are repeatedly deposited on the substrate and patterned as desired. A plurality of ICs are formed on a semiconductor substrate, such as a silicon wafer, in parallel.
Lithographic techniques are used to pattern the device layer or layers. Such techniques use an exposure source to project a light image from a mask or reticle onto a photoresist (resist) layer formed on the surface of the wafer. The light illuminates the resist layer, exposing it with the desired pattern. Depending on whether a positive or negative tone resist is used, the exposed or unexposed portions of the resist layer are removed. The portions not protected by the resist are then etched to form the features in the substrate.
To ensure that the features are formed in the desired location on the wafer, the wafer and reticle need to be properly aligned. To facilitate alignment, alignment marks are formed on the wafer and reticle. The alignment marks generate a diffraction pattern when scanned by a laser alignment source from an alignment system. Typically, the alignment source is part of the lithographic tool, such as a stepper. The diffraction pattern is reflected and sensed by an alignment sensor which records the position of the marks. The stepper shifts the wafer stage (e.g., x, y and/or rotationally) until the wafer and reticle marks overlay each other.
During a process flow for fabricating an IC, numerous lithographic steps are required. Overlay measurements are typically performed to verify alignment of the different layers. Alignment or overlay marks are formed on the different layers to facilitate overlay measurements. The relative positions of the overlay marks on the different layers are measured. The sets of overlay marks are positioned such that they overlay each other if the layers are properly aligned.
FIG. 1 shows a conventional alignment mark 101. The alignment mark comprises plurality of straight lines 120 separated by spaces 130, producing an alignment mark grating. However, such conventional alignment mark designs suffer from poor signal-to-noise ratio due to variations in the stack of layers on the wafer. Moreover, this problem is exacerbated by the fact that processes are optimized for performance and not irradiance or detection of alignment marks. Alignment mark integrity is thereby compromised which adversely affects overlay measurement capabilities.
From the foregoing discussion, it is desirable to provide an alignment mark design which improves overlay measurement performance.